UIS avalanche damage mode of power MOSFET

UIS avalanche damage mode of power MOSFET

There are three modes of UIS avalanche damage in power MOSFETs: thermal damage, parasitic transistor conduction damage, and VGS spike false triggering conduction damage.

1. Thermal damage

Under the action of power pulses, power MOSFETs enter the working state of UIS avalanche. As the VDS voltage increases, the electric field from the body to the epi junction also increases. When the field strength reaches the critical value (approximately 3 * e5V/cm in silicon), the avalanche multiplication of charge carriers occurs, resulting in a sudden and sharp increase in current. Avalanche multiplication is not a process of damage. In this process, the increase in power consumption leads to an increase in the junction temperature of the silicon wafer. When the junction temperature rises to the critical value allowed by the characteristics of the silicon wafer, failure will occur.

Traditional planar process power MOSFETs, due to their low cell density, simple manufacturing process, and good cell consistency, can effectively conduct the heat generated by the channel between cells. In most cases, the temperature difference between different regions of the silicon wafer is small, and the damage caused by avalanche process is completely determined by the overall thermal breakdown of the silicon wafer.

During the production and cutting process, there may be stress damage at the edge of power MOSFETs, resulting in large leakage currents and a decrease in breakdown voltage and long-term stability, as well as a decrease in avalanche capability. Structurally, this can be improved by adding field plates or field loops at the edge.

2. Parasitic transistor conduction damage

During the avalanche process of power MOSFET in UIS, as the voltage increases, the electric field from the body to the epi junction also increases. When the field strength reaches a critical value (approximately 3 * e5V/cm in silicon), the avalanche multiplication of charge carriers occurs, resulting in a sudden and sharp increase in current. At the same time, the heat generated charge carriers form in the epitaxial region, generating hotspots.

The internal structure of a power MOSFET has a parasitic transistor, and the path through which current flows includes the path through which hole current flows IH (IH=ID), which may generate high current density. When VBE=IH * (Rp+Rc)>0.7V, the increase in base current IB and the amplification effect of the transistor cause local parasitic transistors to conduct. Among them, Rp is the squeezing resistance of the lower body of the source, and Rc is the connecting resistance.

After this state occurs, the gate can no longer turn off the current of the MOSFET. Due to local inconsistency, weak cells with parasitic transistors have a negative temperature coefficient when the NPN transistor conducts. Under high temperature and high current conditions, the NPN transistor conducts, causing higher temperature cells to share more current. As a result, a current fuse effect occurs in weak cells, leading to loss of control.

Even short low-energy high-voltage pulses only fail when the current density exceeds the critical level. The high Rp and Rc values reduce the UIS capability. In the new generation of power MOSFET structures, such as high voltage super junction SJ and low medium voltage shield gate SGT processes, high current density cell structures are used, and the transistor amplification factor is very high. Although the Rp value is not large, Rp and Rc both increase with increasing temperature, and the emitter base turn-on voltage VBE decreases with increasing temperature, resulting in a decrease in UIS capability with increasing temperature.

At the same time, the new generation of structural processes is complex, increasing the inconsistency of unit performance; High unit density and mutual heating can easily lead to localized concentration of heat generation and temperature rise, thereby affecting the avalanche capability of UIS.

In addition, during the reverse recovery period of the diode in the body, the rapid rise in the drain voltage will cause parasitic bipolar transistors to conduct, resulting in a rapid increase in drain voltage. However, the recombination of minority carriers leads to a positive bias of the emitter junction, causing the transistor to conduct and the device to be damaged. We will discuss it further in the context of diodes in the future.

When the inductance value decreases, the current rises quickly, and the heat generated by the avalanche of the power MOSFET cannot be dissipated in time due to the delay effect of the internal heat capacity, which makes it easier for local units to overheat and be damaged, resulting in a decrease in avalanche energy.

3. VGS spike mistakenly triggers conduction damage

During the UIS avalanche process, the temperature of the silicon wafer increases and the threshold of VGS sharply decreases. At the same time, during the avalanche process, the voltage of VDS couples to the G pole, and the voltage VGS generated on G and S is higher than the threshold. The MOSFET is mistakenly triggered and turned on, causing a transient high current to flow through a local area of the silicon wafer, generating a current fuse effect and damaging the power MOSFET. In this process, the damage mechanism of parasitic transistor conduction is usually superimposed.

In practical applications, UIS avalanche is less likely to fail in this way.

4. What application conditions should consider avalanche energy?

In practical applications, avalanche damage is mostly caused by the combined effects of multiple extreme boundary conditions, such as high temperature, system output short circuit and overload testing, input overvoltage testing, and dynamic aging testing. Overvoltage damage is usually directly understood as avalanche failure damage, because the avalanche process is accompanied by overvoltage phenomena. Only those applications that generate large voltage spikes at the D and S poles of MOSFETs need to consider the avalanche energy of the device.

The energy generated by voltage spikes is mainly determined by inductance and current. For flyback applications, when MOSFET is turned off, a large voltage spike will be generated: VIN+output reflected voltage+leakage inductance. Under normal circumstances, with a clamping circuit, power devices will be de rated, leaving sufficient voltage margin and no problems.

However, under some extreme conditions, when the test output is short circuited during startup or operation, the short-circuit protection is activated, the system is turned off, and then restarted. This process repeats, and when the output is short circuited, the primary inductance may saturate, generating a large current. The clamping circuit may not work properly, and the leakage inductance may produce large spikes, which may cause avalanche damage to the device. Therefore, in such application conditions, the avalanche energy of the device should be considered.

Due to the inductive nature of some motor loads and the generation of significant surge currents during start-up and stall processes, the avalanche energy of the components must also be considered in such applications.