Classification of MOS transistor packaging

According to the installation method on the PCB board, there are two main types of MOS diode packaging: through hole and surface mount.

Insertion type refers to the MOSFET pins passing through the mounting holes on the PCB board and being soldered onto the PCB board. There are three common styles of plug-in packaging: dual in-line package (DIP), transistor outer package (TO), and pin grid array package (PGA).

Plug-in packaging

Surface mount refers to the soldering of MOSFET pins and heat dissipation flanges onto the solder pads on the surface of the PCB board. Typical surface mount packaging includes: transistor outer shape (D-PAK), small outer shape transistor (SOT), small outer shape packaging (SOP), square flat packaging (QFP), plastic encapsulated lead chip carrier (PLCC), etc.

Surface mount packaging

With the development of technology, the use of direct insertion packaging for PCB boards such as motherboards and graphics cards is becoming increasingly rare, and surface mount packaging is being used more frequently.

1. Dual in-line package (DIP)

The DIP package has two rows of pins that need to be inserted into a chip socket with DIP structure. Its derivative is SDIP (Shrink DIP), which is a compact dual input package with a pin density six times higher than DIP.

The DIP packaging structure forms include: multi-layer ceramic DIP, single-layer ceramic DIP, lead frame DIP (including glass ceramic sealing, plastic packaging structure, ceramic low melting glass packaging), etc. The characteristic of DIP packaging is that it can easily achieve through-hole soldering of PCB boards and has good compatibility with motherboards.

However, due to its large packaging area and thickness, and the fact that the pins are easily damaged during insertion and extraction, its reliability is poor; Due to the influence of the manufacturing process, the number of pins generally does not exceed 100. Therefore, in the highly integrated process of the electronics industry, DIP packaging has gradually withdrawn from the historical stage.

2. Transistor outer packaging (TO)

Belonging to early packaging specifications, such as TO-3P, TO-247, TO-92, TO-92L, TO-220, TO-220F, TO-251, etc. are all plug-in packaging designs.

TO-3P/247: It is a commonly used packaging form for medium high voltage and high current MOS transistors. The product has the characteristics of high voltage resistance and strong resistance to breakdown.

TO-220/220V: TO-220F is fully plastic encapsulated and does not require insulation pads when installed on a heat sink; TO-220 is connected to the middle foot with a metal sheet, and an insulation pad should be added when installing the heat sink. These two packaging styles of MOS transistors have similar appearances and can be used interchangeably.

TO-251: This packaged product is mainly designed to reduce costs and shrink product size, and is mainly used in medium voltage high current environments below 60A and high voltage environments below 7N.

TO-92: This package only uses low-voltage MOS transistors (current below 10A, withstand voltage below 60V) and high-voltage 1N60/65 to reduce costs.

In recent years, due to the high soldering cost and inferior heat dissipation performance of plug-in packaging technology compared to surface mount products, the demand for surface mount packaging in the market has continued to increase, leading to the development of TO packaging into surface mount packaging. TO-252 (also known as D-PAK) and TO-263 (D2PAK) are surface mount packaging.

TO Packaging Product Appearance

TO252/D-PAK is a plastic encapsulated surface mount package commonly used for packaging power transistors and voltage regulators, and is currently one of the mainstream packages.

The MOSFET using this packaging method has three electrodes: gate (G), drain (D), and source (S).

The pin of the drain (D) is cut off and not used. Instead, a heat dissipation plate on the back is used as the drain (D), which is directly soldered onto the PCB. On the one hand, it is used to output high current, and on the other hand, it is used to dissipate heat through the PCB; So there are three D-PAK pads on the PCB, and the drain (D) pad is larger.

TO-252/D-PAK package size specifications

TO-263 is a variant of TO-220, mainly designed to improve production efficiency and heat dissipation, supporting extremely high current and voltage, and is more common in medium voltage high current MOS transistors below 150A and above 30V.

In addition to D2PAK (TO-263AB), it also includes styles such as TO263-2, TO263-3, TO263-5, TO263-7, etc., which are subordinate to TO-263, mainly due to differences in the number and distance of lead out feet.

TO-263/D2PAK package size specifications

3. Pin Grid Array Packaging (PGA)

There are multiple square shaped pins inside and outside the PGA (Pin Grid Array Package) chip, and each square shaped pin is arranged at a certain distance along the periphery of the chip. Depending on the number of pins, they can form 2-5 circles. When installing, simply insert the chip into a dedicated PGA socket, which has the advantages of easy insertion and high reliability, and can adapt to higher frequencies.

PGA packaging style

Most of its chip substrates are made of ceramic materials, and some are made of specially made plastic resins. In terms of technology, the pin center distance is usually 2.54mm, and the number of pins ranges from 64 to 447.

The characteristic of this packaging is that the smaller the packaging area (volume), the lower the power consumption (performance) it can withstand, and vice versa, the higher. This packaging form of chip was relatively common in the early days and was mostly used for packaging high-power products such as CPUs. Intel's 80486 and Pentium both use this packaging style; Not widely adopted by MOS transistor manufacturers.

4. Small form factor transistor package (SOT)

SOT (Small Out Line Transistor) is a chip type low-power transistor package, mainly including SOT23, SOT89, SOT143, SOT25 (i.e. SOT23-5), etc., and also derived from SOT323, SOT363/SOT26 (i.e. SOT23-6) and other types, with a smaller volume than TO packages.

SOT packaging type

SOT23 is a commonly used transistor packaging form, with three wing shaped pins, namely collector, emitter, and base, listed on both sides of the long side of the component, where the emitter and base are on the same side. It is commonly used in low-power transistors, field-effect transistors, and composite transistors with resistance networks. It has good strength but poor solderability, and its appearance is shown in Figure (a) below.

SOT89 has three short pins distributed on one side of the transistor, and the other side is a metal heat sink connected to the base to increase heat dissipation capacity. It is commonly used in silicon power surface mount transistors and is suitable for higher power applications. Its appearance is shown in Figure (b) below.

SOT143 has four wing shaped short pins, which are led out from both sides. The wider end of the pins is the collector. This type of package is commonly used in high-frequency transistors, and its appearance is shown in Figure (c) below.

SOT252 belongs to high-power transistors, with three pins leading out from one side. The middle pin, which is shorter and serves as the collector, is connected to the larger pin on the other end. This pin is a copper plate for heat dissipation, and its appearance is shown in Figure (d) below.

Comparison of Common SOT Packaging Appearance

SOT-89 MOSFET with four terminal pins is commonly used on motherboards. The specifications and dimensions are as follows:

SOT-89 MOSFET size specifications (unit: mm)

5. Small form factor packaging (SOP)

SOP (Small Out Line Package) is one of the surface mount packages, also known as SOL or DFP, with pins extending from both sides of the package in a seagull shaped (L-shaped) pattern. There are two types of materials: plastic and ceramic.

SOP packaging standards include SOP-8, SOP-16, SOP-20, SOP-28, etc. The number after SOP represents the number of pins. The SOP packaging of MOSFETs mostly adopts the SOP-8 specification, and the industry often omits "P" and abbreviates it as SO (Small Out Line).

SOP-8 packaging size

SO-8 is packaged in plastic and lacks a heat dissipation substrate, resulting in poor heat dissipation. It is generally used for low-power MOSFETs.

Later, standard specifications such as TSOP (Thin Small Form factor Package), VSOP (Very Small Form factor Package), SSOP (Reduced Form factor SOP), TSSOP (Thin Reduced Form factor SOP) were gradually derived; TSOP and TSSOP are commonly used in MOSFET packaging.

SOP derived specifications commonly used for MOS transistors

6. Square Flat Package (QFP)

QFP (Plastic Quad Flat Package) chips have very small distances between pins and thin pins, which are generally used in large-scale or ultra large integrated circuits, with a pin count of generally over 100.

Chips packaged in this form must be soldered to the motherboard using SMT surface mount technology. This packaging method has four major characteristics:

① Suitable for SMD surface mount technology to install wiring on PCB circuit boards;

② Suitable for high-frequency use;

③ Easy to operate and highly reliable;

④ The ratio between chip area and packaging area is relatively small.

Like the PGA packaging method, this packaging method wraps the chip inside a plastic package, which cannot timely dissipate the heat generated by the chip during operation, limiting the improvement of MOSFET performance; Moreover, the plastic packaging itself increases the size of the device, which does not meet the requirements of semiconductor development towards light, thin, short, and small direction; In addition, this type of packaging method is based on a single chip, which has problems of low production efficiency and high packaging costs.

Therefore, QFP is more suitable for digital logic LSI circuits such as microprocessors/door displays, as well as for packaging analog LSI circuit products such as VTR signal processing and audio signal processing.

7. Quad Leadless Flat Packaging (QFN)

The QFN (Quad Flat Non led package) package is equipped with electrode contacts on all four sides. Due to the lack of leads, the mounting exhibits the characteristics of smaller area and lower height than QFP; Among them, ceramic QFN is also known as LCC (Leadless Chip Carriers), while low-cost plastic QFN using glass epoxy resin printed substrate is called plastic LCC, PCLC, P-LCC, etc.

It is an emerging surface mount chip packaging technology with small pad size, small volume, and plastic as the sealing material.

QFN is mainly used for integrated circuit packaging, and MOSFETs will not be used. However, due to Intel's proposal to integrate drivers and MOSFET solutions, a DrMOS was launched using the QFN-56 package ("56" refers to 56 connection pins on the back of the chip).

It should be noted that QFN packaging and ultra-thin small form factor packaging (TSSOP) have the same external lead configuration, but their size is 62% smaller than TSSOP. According to QFN modeling data, its thermal performance has improved by 55% compared to TSSOP packaging, and its electrical performance (inductance and capacitance) has improved by 60% and 30% respectively compared to TSSOP packaging. The biggest disadvantage is the high difficulty of repair.

DrMOS packaged in QFN-56

Traditional split DC/DC buck switching power supplies cannot meet the requirements for higher power density, nor can they solve the problem of parasitic parameter effects at high switching frequencies.

With the innovation and progress of technology, integrating drivers and MOSFETs together to build multi chip modules has become a reality. This integration method can save considerable space and improve power density. By optimizing drivers and MOSFETs, power efficiency and high-quality DC current can be improved. This is the DrMOS integrated driver IC.

2nd generation DrMOS

After QFN-56 footless packaging, DrMOS has a very low thermal impedance; By utilizing internal wire bonding and copper clip design, external PCB wiring can be minimized to the greatest extent possible, thereby reducing inductance and resistance.

In addition, the use of deep trench silicon MOSFET technology can significantly reduce conduction, switching, and gate charge losses; And it is compatible with multiple controllers, can achieve different working modes, and supports active phase switching mode APS (Auto Phase Switching).

8. Plastic encapsulated lead chip carrier (PLCC)

The PLCC (Plastic Quad Flat Package) has a square shape and is much smaller in size than DIP packages. It has 32 pins and pins on all sides. The pins are led out from the four sides of the package in a T-shaped shape and are made of plastic.

The center distance of its pins is 1.27mm, and the number of pins varies from 18 to 84. The J-shaped pins are not easily deformed and are easier to operate than QFP, but the appearance inspection after soldering is more difficult. PLCC packaging is suitable for installing wiring on PCBs using SMT surface mount technology, and has the advantages of small external dimensions and high reliability.

PLCC packaging is quite common, used for circuits such as logic LSI, DLD (or programmable logic devices), and is commonly used in motherboard BIOS. However, it is currently less common in MOS transistors.

PLCC packaging style

Packaging and improvement of mainstream enterprises

Due to the development trend of low voltage and high current in CPUs, MOSFETs are required to have high output current, low on resistance, low heat generation, fast heat dissipation, and small size. MOSFET manufacturers not only improve chip production technology and processes, but also continuously improve packaging technology. Based on compatibility with standard external specifications, they propose new packaging shapes and register trademark names for their newly developed packaging.