Working principle of P-channel MOS transistor

During normal operation, the substrate of a P-channel enhanced MOS transistor must be connected to the source, and the voltage Vds at the drain center should be negative to ensure that the PN junction between the two P regions and the substrate is reverse biased. At the same time, in order to form a conductive channel near the top surface of the substrate, the voltage Vgs between the gate and the source should also be negative.

1. When the conductive channel is formed with Vds ≠ O and a negative voltage is applied between DS, a drain current Id will flow between the source and drain, and Id will increase with Vds.

The voltage drop generated by Id along the channel causes the voltage between each point on the channel and the gate to no longer be equal, which weakens the effect of the negative charge electric field in the gate and gradually narrows the channel from the drain to the source. When Vds increases to Vgd=Vgs (TH), the channel exhibits pre pinch off near the drain.

2. When Vds=0, a negative voltage Vgs is applied between the gate and source. Due to the presence of the insulating layer, there is no current, but the metal gate is charged and accumulates negative charges. The multi carrier electrons in the N-type semiconductor are repelled by the negative charges and move towards the body, leaving positively charged ions on the surface, forming a depletion layer. As the negative voltage between G and S increases, the depletion layer widens.

When Vgs increases to a certain value, the holes (minority carriers) in the substrate are absorbed by the negative charges in the gate to the surface, forming a P-type thin layer between the depletion layer and the insulation layer, called the inversion layer.

This inversion layer forms a conductive channel between the drain and source, and the Vgs at this point is called the turn-on voltage Vgs (th). As Vgs increases to Vgs (th), the more holes induced on the substrate surface, the wider the inversion layer, while the width of the depletion layer remains unchanged. In this way, the width of the conductive channel can be controlled by the size of Vgs.

When the Vgs of PMOS is less than a certain value, it will conduct, which is suitable for situations where the source is connected to VCC (high-end driving). It should be noted that Vgs refers to the voltage between the gate G and the source S, that is, the gate conducts when it is below a certain voltage of the power supply, not the voltage relative to ground.

However, due to the high internal resistance of PMOS conduction, it is only suitable for low-power situations. However, high power still uses N-channel MOS transistors.
During normal operation, the substrate of a P-channel enhanced MOS transistor must be connected to the source, and the voltage Vds at the drain center should be negative to ensure that the PN junction between the two P regions and the substrate is reverse biased. At the same time, in order to form a conductive channel near the top surface of the substrate, the voltage Vgs between the gate and the source should also be negative.

1. When the conductive channel is formed with Vds ≠ O and a negative voltage is applied between DS, a drain current Id will flow between the source and drain, and Id will increase with Vds.

 The voltage drop generated by Id along the channel causes the voltage between each point on the channel and the gate to no longer be equal, which weakens the effect of the negative charge electric field in the gate and gradually narrows the channel from the drain to the source. When Vds increases to Vgd=Vgs (TH), the channel exhibits pre pinch off near the drain.

 2. When Vds=0, a negative voltage Vgs is applied between the gate and source. Due to the presence of the insulating layer, there is no current, but the metal gate is charged and accumulates negative charges. The multi carrier electrons in the N-type semiconductor are repelled by the negative charges and move towards the body, leaving positively charged ions on the surface, forming a depletion layer. As the negative voltage between G and S increases, the depletion layer widens.

 When Vgs increases to a certain value, the holes (minority carriers) in the substrate are absorbed by the negative charges in the gate to the surface, forming a P-type thin layer between the depletion layer and the insulation layer, called the inversion layer.

 This inversion layer forms a conductive channel between the drain and source, and the Vgs at this point is called the turn-on voltage Vgs (th). As Vgs increases to Vgs (th), the more holes induced on the substrate surface, the wider the inversion layer, while the width of the depletion layer remains unchanged. In this way, the width of the conductive channel can be controlled by the size of Vgs.

 When the Vgs of PMOS is less than a certain value, it will conduct, which is suitable for situations where the source is connected to VCC (high-end driving). It should be noted that Vgs refers to the voltage between the gate G and the source S, that is, the gate conducts when it is below a certain voltage of the power supply, not the voltage relative to ground.

 However, due to the high internal resistance of PMOS conduction, it is only suitable for low-power situations. However, high power still uses N-channel MOS transistors.